For a high power semiconductor device with a U-shape gate, such as U-shape Metal Oxide Semiconductor Field Effect Transistors (UMOSFETs) or Trench Insulated Gate Bipolar Transistors (IGBTs), the UMOS gate corners may be exposed to a high electrical field under the OFF state providing increased field stress. This increased field stress can degrade the device blocking rating significantly and may result in a low manufacturing yield. Even if a junction with opposite polarity to the drift region, a junction gate, is introduced to relieve the field stress, a narrow gap between the junction gates may cause the depletion layer to pinch off and reduce forward conduction current capability. Moreover, the introduction of a gate junction can cause depletion pinching off between the gate junction and base junction in the MOS channel, if the spacing is not adequate. Typically, adequate spacing requires deeper mesa etching, which may increase process complexity. For high power devices, the drift region is normally lightly doped, thus the spacing between the junction and channel must be more than several microns, which creates significant difficulties during fabrication, and specifically in an etching process for such a deep mesa. This problem is compounded when using Silicon Carbide (SiC) or other hard semiconductor materials. Hence, there remains a need in the art for a UMOS gate structure that addresses these and other deficiencies in a cost effective manner.